A CMI code is a code in which data "0" is represented by "01", and data "1" is represented by "00" and "11" alternately used, wherein each bit of the codes "01", "00" and "11" is allocated to a period which is defined by dividing a time slot by two.
In a method for sampling a clock included in a CMI code to detect a phase difference between a VCO clock and the CMI code, a ceramic filter is used. However, this method has disadvantages in that size can not be small, and cost can not be reduced. For these disadvantages, a PLL circuit is proposed to be realized in an integrated circuit including a phase comparator, a loop filter and a VCO. In the PLL circuit, the phase comparator comprises an edge detecting circuit for detecting rise-up and fall-down of a CMI clock to provide a pulse signal, a first D-flip flop for providing two complementary signals each having a pulse width equal to a period of a VCO clock by receiving the VCO clock a second D-flip flop for providing a phase signal of the CMI code by receiving the pulse signal and one of the two complementary signal, and an exclusive OR gate for providing a phase difference signal in accordance with an exclusive OR logic calculation between the phase signal of the CMI code and the remaining one of the two complementary signal which is a phase signal of the VCO clock.
In the PLL circuit, the phase difference signal which is obtained from the exclusive OR circuit is supplied to the low-pass filter, from which a controlled DC voltage is applied to the VCO, so that a frequency of the VCO clock is controlled dependently on a level of the controlled DC voltage.
However, the phase comparator has a disadvantage in that the phase difference signal is not obtained on condition that the CMI code is of "00" and "11" to express CMI data "1" and "1", because the signal of rise-up and fall-down of the CMI code has a period equal to two periods of the VCO clock, thereby resulting that the phase signal of the CMI code is kept to be high for the duration of the CMI data "1", that is, the CMI code "00" and "11". Consequently, a loop gain is lowered to increase jitter. As a matter of course, no generation of a phase difference signal results in the stepping out of synchronism. Further, there are disadvantages in that a precision is required for a relation between a phase difference and a pulse width of a phase difference signal, because the phase difference is converted to the pulse width of the phase difference signal, and in that jitter occurs, when noise is superposed on the phase difference signal to change the pulse width of the phase difference signal.